LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY addressbuff IS
   PORT(
       CLOCK ,table_ack:  IN STD_LOGIC;
       portChoice : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
	   src_mux1, src_mux2,src_mux3,src_mux4  : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
	   des_mux1, des_mux2,des_mux3,des_mux4 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
	   srcPort : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
	   ready: BUFFER STD_LOGIC;
	   srcAddress : OUT STD_LOGIC_VECTOR(47 DOWNTO 0):="000000000000000000000000000000000000000000000000";
	   desAddress : OUT STD_LOGIC_VECTOR(47 DOWNTO 0):="000000000000000000000000000000000000000000000000"
       );
END addressbuff;

ARCHITECTURE structural OF addressbuff IS
COMPONENT AddressMUX IS
   PORT(
       CLOCK :  IN STD_LOGIC;
       portChoice : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
	   src_mux1, src_mux2,src_mux3,src_mux4  : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
	   des_mux1, des_mux2,des_mux3,des_mux4 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
	   srcPort : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
	   srcAddress : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
	   desAddress : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
       );
END COMPONENT;
COMPONENT counter IS
	PORT
	(
		clock		: IN STD_LOGIC ;
		sclr		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
	);

END COMPONENT;
SIGNAL srcpart,despart:  STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL srcpart1,despart1:  STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL count: STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL srcPort1: STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL srcpart2,despart2:  STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL srcpart3,despart3: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL srcpart4,despart4:  STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL srcpart5,despart5:  STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL srcpart6,despart6:  STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL sclr:  STD_LOGIC;
SIGNAL next_cycle:  STD_LOGIC:='1';

BEGIN
-- This doesn't compile, fix this
-- mux11: AddressMUX PORT MAP(CLOCK, portChoice, src_mux1, src_mux2, src_mux3, src_mux4, des_mux1, des_mux2, des_mux3, des_mux4, srcPort1, srcpart, despart);

counter1: counter PORT MAP(CLOCK, sclr , count);


PROCESS(srcpart,despart,count,table_ack)
BEGIN
if (count="000" ) then 
sclr<='0';
srcpart1<=srcpart;
despart1<=despart;
ready<='0';
next_cycle<='0';
elsif (count="001" ) then 
srcpart2<=srcpart;
despart2<=despart;
ready<='0';
next_cycle<='0';
elsif (count="010" ) then
srcpart3<=srcpart;
despart3<=despart;
ready<='0';
next_cycle<='0';
elsif (count="011" ) then
srcpart4<=srcpart;
despart4<=despart;
ready<='0';
next_cycle<='0';
elsif (count="100" ) then
srcpart5<=srcpart;
despart5<=despart;
ready<='0';
next_cycle<='0';
elsif (count="101" ) then
srcpart6<=srcpart;
despart6<=despart;
ready<='0';
next_cycle<='0';
else
sclr<='1';
if(table_ack='1' )then
ready<='1';
next_cycle<='1';
else
next_cycle<='0';
ready<='0';
end if;
end if;
END PROCESS;

PROCESS(srcpart1,despart1,srcpart2,despart2,srcpart3,despart3,srcpart4,despart4,srcpart5,despart5,srcpart6,despart6,count)
BEGIN
if (  count="110" and next_cycle<='1' and table_ack='1' ) then 
srcAddress(7 DOWNTO 0)<=srcpart1;
desAddress(7 DOWNTO 0)<=despart1;
srcAddress(15 DOWNTO 8)<=srcpart2;
desAddress(15 DOWNTO 8)<=despart2;
srcAddress(23 DOWNTO 16)<=srcpart3;
desAddress(23 DOWNTO 16)<=despart3;
srcAddress(31 DOWNTO 24)<=srcpart4;
desAddress(31 DOWNTO 24)<=despart4;
srcAddress(39 DOWNTO 32)<=srcpart5;
desAddress(39 DOWNTO 32)<=despart5;
srcAddress(47 DOWNTO 40)<=srcpart6;
desAddress(47 DOWNTO 40)<=despart6;
END IF;
srcPort<=portChoice;
END PROCESS;

END structural;


